Pacman Board Theory - Revision history

Brad at 03:10, 14 August 2012

2012-08-14T03:10:25Z

← Older revision		Revision as of 11:10, 14 August 2012
Line 5:		Line 5:
	schematics (not just to confuse you).</p>		schematics (not just to confuse you).</p>

	~~__TOC__~~		__FORCETOC__

	== Sync and Timing Signal Generation ==		== Sync and Timing Signal Generation ==

Brad at 03:09, 14 August 2012

2012-08-14T03:09:47Z

← Older revision		Revision as of 11:09, 14 August 2012
Line 4:		Line 4:
	<p>After searching the net for info while fixing a stack of dead pacman boards, I couldn't find any documentation on the video circuitry. This document is an attempt to rectify the problem. Since pacman uses a rotated monitor, the term horizontal will refer to things that appear on the vertical axis and vice-versa, so that the description will match the labeling on the		<p>After searching the net for info while fixing a stack of dead pacman boards, I couldn't find any documentation on the video circuitry. This document is an attempt to rectify the problem. Since pacman uses a rotated monitor, the term horizontal will refer to things that appear on the vertical axis and vice-versa, so that the description will match the labeling on the
	schematics (not just to confuse you).</p>		schematics (not just to confuse you).</p>

			__TOC__

	== Sync and Timing Signal Generation ==		== Sync and Timing Signal Generation ==

Brad at 03:08, 14 August 2012

2012-08-14T03:08:23Z

← Older revision		Revision as of 11:08, 14 August 2012
Line 5:		Line 5:
	schematics (not just to confuse you).</p>		schematics (not just to confuse you).</p>

	=== Sync and Timing Signal Generation ===		== Sync and Timing Signal Generation ==

	The count sequences for the horizontal and vertical timing signals are listed at the end.		The count sequences for the horizontal and vertical timing signals are listed at the end.
Line 19:		Line 19:
	VBLANK is generated by a flipflop at 5M. VBLANK is cleared when 16V goes high when 32V, 64V, and 128V, near the end of the count sequence. It is reset when 16H goes high when 32V, 64V, and 128V are all low near the beginning of the count sequence. The vertical blanking period lasts for 38 HSYNC cycles leaving 224 counts for data (thus the 224 line vertical resolution).		VBLANK is generated by a flipflop at 5M. VBLANK is cleared when 16V goes high when 32V, 64V, and 128V, near the end of the count sequence. It is reset when 16H goes high when 32V, 64V, and 128V are all low near the beginning of the count sequence. The vertical blanking period lasts for 38 HSYNC cycles leaving 224 counts for data (thus the 224 line vertical resolution).

	=== <p>Memory Map</p> ===		== <p>Memory Map</p> ==

	Sure there's more to it, but this is all the video system cares about.		Sure there's more to it, but this is all the video system cares about.
Line 31:		Line 31:
	Byte 1: Color Code		Byte 1: Color Code

	=== <p>Sync Bus Controller</p> ===		== <p>Sync Bus Controller</p> ==

	The sync bus controller interfaces the external devices to the processor. The address and data bus are connected to the roms directly, but for ram and IO port access the sync bus controller gets in the way. An important thing to note is that the 6M* input to the SBC trails the 6Mhz used to generate the timing clocks by 1/3 phase, so the edge occurs during each level of 1H. The /CS line is asserted during a /MREQ with A14 high, during a non-refresh cycle (/RFSH high).		The sync bus controller interfaces the external devices to the processor. The address and data bus are connected to the roms directly, but for ram and IO port access the sync bus controller gets in the way. An important thing to note is that the 6M* input to the SBC trails the 6Mhz used to generate the timing clocks by 1/3 phase, so the edge occurs during each level of 1H. The /CS line is asserted during a /MREQ with A14 high, during a non-refresh cycle (/RFSH high).
Line 37:		Line 37:
	To handle interrupts, Pacman uses the I interrupt regiester to store the high 8 bits of the interrupt vector address and writes the low 8 bits to 0x00, which stores it in the register at U7. During a mode 0 interrupt, /IORQ and /M1 are asserted, and the stored value is put back onto the data bus, and used as the low 8 bits of the of interrupt vector.		To handle interrupts, Pacman uses the I interrupt regiester to store the high 8 bits of the interrupt vector address and writes the low 8 bits to 0x00, which stores it in the register at U7. During a mode 0 interrupt, /IORQ and /M1 are asserted, and the stored value is put back onto the data bus, and used as the low 8 bits of the of interrupt vector.

	=== <p>VRAM Addresser</p> ===		== <p>VRAM Addresser</p> ==

	The VRAM addresser determines the address to be accessed by the video output circuitry based on the values of the horizontal and vertical timing signals. The address is enabled by /2H. When 2H is low, the CPU controls the bus. When 2H is high, the video generator controls it.		The VRAM addresser determines the address to be accessed by the video output circuitry based on the values of the horizontal and vertical timing signals. The address is enabled by /2H. When 2H is low, the CPU controls the bus. When 2H is high, the video generator controls it.
Line 51:		Line 51:
	43C4-43FB : Level area		43C4-43FB : Level area

	===Horizontal Timing Signals ===		== Horizontal Timing Signals ==

	~ (382 lines, 96 blanked, 286 data)<br>		~ (382 lines, 96 blanked, 286 data)<br>
Line 119:		Line 119:
	111111110 011<br>		111111110 011<br>

	=== Vertical Timing Signals ===		== Vertical Timing Signals ==

	~1 ~ (262 rows, 38 blanked, 224 normal)<br>		~1 ~ (262 rows, 38 blanked, 224 normal)<br>
Line 171:		Line 171:
	111111110 0<br>		111111110 0<br>

	=== Sprites: ===		== Sprites: ==

	4ff0-4fff 8 pairs of two bytes:<br>		4ff0-4fff 8 pairs of two bytes:<br>
Line 181:		Line 181:
	H64 H32 H16 H4 (?)<br>		H64 H32 H16 H4 (?)<br>

	=== Addressed from VRA during: ===		== Addressed from VRA during: ==

	~256H = 0 (74257 select input)<br>		~256H = 0 (74257 select input)<br>
	16H != 32H or 32H != 64H (74157 select input)		16H != 32H or 32H != 64H (74157 select input)

Brad at 03:06, 14 August 2012

2012-08-14T03:06:54Z

← Older revision		Revision as of 11:06, 14 August 2012
Line 121:		Line 121:
	=== Vertical Timing Signals ===		=== Vertical Timing Signals ===

	~1 ~ (262 rows, 38 blanked, 224 normal)		~1 ~ (262 rows, 38 blanked, 224 normal)<br>
	V2631 V		V2631 V<br>
	S84268421 B		S84268421 B<br>
			<br>
	011111001 0		011111001 0<br>
	011111010 0		011111010 0<br>
	011111011 0		011111011 0<br>
	011111100 0		011111100 0<br>
	011111101 0		011111101 0<br>
	011111110 0		011111110 0<br>
	011111111 0		011111111 0<br>
	100000--- 0		100000--- 0<br>
	100001--- 0		100001--- 0<br>
	100010--- 1 0000 0100 00000		100010--- 1 0000 0100 00000<br>
	100011--- 1		100011--- 1<br>
	100100--- 1		100100--- 1<br>
	100101--- 1		100101--- 1<br>
	100110--- 1		100110--- 1<br>
	100111--- 1		100111--- 1<br>
	101000--- 1		101000--- 1<br>
	101001--- 1		101001--- 1<br>
	101010--- 1		101010--- 1<br>
	101011--- 1		101011--- 1<br>
	101100--- 1		101100--- 1<br>
	101101--- 1		101101--- 1<br>
	101110--- 1		101110--- 1<br>
	101111--- 1		101111--- 1<br>
	110000--- 1		110000--- 1<br>
	110001--- 1		110001--- 1<br>
	110010--- 1		110010--- 1<br>
	110011--- 1		110011--- 1<br>
	110100--- 1		110100--- 1<br>
	110101--- 1		110101--- 1<br>
	110110--- 1		110110--- 1<br>
	110111--- 1		110111--- 1<br>
	111000--- 1		111000--- 1<br>
	111001--- 1		111001--- 1<br>
	111010--- 1		111010--- 1<br>
	111011--- 1		111011--- 1<br>
	111100--- 1		111100--- 1<br>
	111101--- 1 0011 1011 1111		111101--- 1 0011 1011 1111<br>
	111110--- 0		111110--- 0<br>
	111111000 0		111111000 0<br>
	111111001 0		111111001 0<br>
	111111010 0		111111010 0<br>
	111111011 0		111111011 0<br>
	111111100 0		111111100 0<br>
	111111101 0		111111101 0<br>
	111111110 0		111111110 0<br>

	=== Sprites: ===		=== Sprites: ===

	4ff0-4fff 8 pairs of two bytes:		4ff0-4fff 8 pairs of two bytes:<br>
	Byte 1: sprite image number (bits 2-7), Y flip (bit 0), X flip (bit 1);		Byte 1: sprite image number (bits 2-7), Y flip (bit 0), X flip (bit 1);<br>
	Byte 2: the color #		Byte 2: the color #<br>

	0100 1111 1111 x x x x		0100 1111 1111 x x x x<br>
	^ ^ ^ ^		^ ^ ^ ^<br>
	H64 H32 H16 H4 (?)		H64 H32 H16 H4 (?)<br>

	=== Addressed from VRA during: ===		=== Addressed from VRA during: ===

	~256H = 0 (74257 select input)		~256H = 0 (74257 select input)<br>
	16H != 32H or 32H != 64H (74157 select input)		16H != 32H or 32H != 64H (74157 select input)

Brad at 03:05, 14 August 2012

2012-08-14T03:05:39Z

← Older revision		Revision as of 11:05, 14 August 2012
Line 53:		Line 53:
	===Horizontal Timing Signals ===		===Horizontal Timing Signals ===

	~ (382 lines, 96 blanked, 286 data)		~ (382 lines, 96 blanked, 286 data)<br>
	21 ~~		21 ~~<br>
	52631 HHH		52631 HHH<br>
	684268421 BBS		684268421 BBS<br>
			<br>
	010000001 011		010000001 011<br>
	010000010 011		010000010 011<br>
	010000011 011		010000011 011<br>
	010000100 011		010000100 011<br>
	010000101 011		010000101 011<br>
	010000110 011		010000110 011<br>
	010000111 011		010000111 011<br>
	010001--- 011		010001--- 011<br>
	010010--- 101		010010--- 101<br>
	010011--- 101		010011--- 101<br>
	010100--- 101		010100--- 101<br>
	010101--- 101		010101--- 101<br>
	010110--- 100		010110--- 100<br>
	010111--- 100		010111--- 100<br>
	011000--- 100		011000--- 100<br>
	011001--- 100		011001--- 100<br>
	011010--- 101		011010--- 101<br>
	011011--- 101		011011--- 101<br>
	011100--- 101		011100--- 101<br>
	011101--- 101		011101--- 101<br>
	011110--- 011		011110--- 011<br>
	011111--- 011		011111--- 011<br>
	100000--- 011		100000--- 011<br>
	100001--- 011		100001--- 011<br>
	100010--- 011		100010--- 011<br>
	100011--- 011		100011--- 011<br>
	100100--- 011		100100--- 011<br>
	100101--- 011		100101--- 011<br>
	100110--- 011		100110--- 011<br>
	100111--- 011		100111--- 011<br>
	101000--- 011		101000--- 011<br>
	101001--- 011		101001--- 011<br>
	101010--- 011		101010--- 011<br>
	101011--- 011		101011--- 011<br>
	101100--- 011		101100--- 011<br>
	101101--- 011		101101--- 011<br>
	101110--- 011		101110--- 011<br>
	101111--- 011		101111--- 011<br>
	100000--- 011		100000--- 011<br>
	100001--- 011		100001--- 011<br>
	100010--- 011		100010--- 011<br>
	100011--- 011		100011--- 011<br>
	100100--- 011		100100--- 011<br>
	100101--- 011		100101--- 011<br>
	100110--- 011		100110--- 011<br>
	101111--- 011		101111--- 011<br>
	111000--- 011		111000--- 011<br>
	111001--- 011		111001--- 011<br>
	111010--- 011		111010--- 011<br>
	111011--- 011		111011--- 011<br>
	111100--- 011		111100--- 011<br>
	111101--- 011		111101--- 011<br>
	111110--- 011		111110--- 011<br>
	111111000 011		111111000 011<br>
	111111001 011		111111001 011<br>
	111111010 011		111111010 011<br>
	111111011 011		111111011 011<br>
	111111100 011		111111100 011<br>
	111111101 011		111111101 011<br>
	111111110 011		111111110 011<br>



	=== Vertical Timing Signals ===		=== Vertical Timing Signals ===

Brad at 03:04, 14 August 2012

2012-08-14T03:04:14Z

← Older revision		Revision as of 11:04, 14 August 2012
Line 50:		Line 50:
	4040-43BF : Screen area		4040-43BF : Screen area
	43C4-43FB : Level area		43C4-43FB : Level area

			===Horizontal Timing Signals ===

			~ (382 lines, 96 blanked, 286 data)
			21 ~~
			52631 HHH
			684268421 BBS

			010000001 011
			010000010 011
			010000011 011
			010000100 011
			010000101 011
			010000110 011
			010000111 011
			010001--- 011
			010010--- 101
			010011--- 101
			010100--- 101
			010101--- 101
			010110--- 100
			010111--- 100
			011000--- 100
			011001--- 100
			011010--- 101
			011011--- 101
			011100--- 101
			011101--- 101
			011110--- 011
			011111--- 011
			100000--- 011
			100001--- 011
			100010--- 011
			100011--- 011
			100100--- 011
			100101--- 011
			100110--- 011
			100111--- 011
			101000--- 011
			101001--- 011
			101010--- 011
			101011--- 011
			101100--- 011
			101101--- 011
			101110--- 011
			101111--- 011
			100000--- 011
			100001--- 011
			100010--- 011
			100011--- 011
			100100--- 011
			100101--- 011
			100110--- 011
			101111--- 011
			111000--- 011
			111001--- 011
			111010--- 011
			111011--- 011
			111100--- 011
			111101--- 011
			111110--- 011
			111111000 011
			111111001 011
			111111010 011
			111111011 011
			111111100 011
			111111101 011
			111111110 011



			=== Vertical Timing Signals ===

			~1 ~ (262 rows, 38 blanked, 224 normal)
			V2631 V
			S84268421 B

			011111001 0
			011111010 0
			011111011 0
			011111100 0
			011111101 0
			011111110 0
			011111111 0
			100000--- 0
			100001--- 0
			100010--- 1 0000 0100 00000
			100011--- 1
			100100--- 1
			100101--- 1
			100110--- 1
			100111--- 1
			101000--- 1
			101001--- 1
			101010--- 1
			101011--- 1
			101100--- 1
			101101--- 1
			101110--- 1
			101111--- 1
			110000--- 1
			110001--- 1
			110010--- 1
			110011--- 1
			110100--- 1
			110101--- 1
			110110--- 1
			110111--- 1
			111000--- 1
			111001--- 1
			111010--- 1
			111011--- 1
			111100--- 1
			111101--- 1 0011 1011 1111
			111110--- 0
			111111000 0
			111111001 0
			111111010 0
			111111011 0
			111111100 0
			111111101 0
			111111110 0

			=== Sprites: ===

			4ff0-4fff 8 pairs of two bytes:
			Byte 1: sprite image number (bits 2-7), Y flip (bit 0), X flip (bit 1);
			Byte 2: the color #

			0100 1111 1111 x x x x
			^ ^ ^ ^
			H64 H32 H16 H4 (?)

			=== Addressed from VRA during: ===

			~256H = 0 (74257 select input)
			16H != 32H or 32H != 64H (74157 select input)

Brad at 03:02, 14 August 2012

2012-08-14T03:02:21Z

← Older revision		Revision as of 11:02, 14 August 2012
Line 1:		Line 1:
	== Pacman Video Circuitry Theory of Operations ==		=== Pacman Video Circuitry Theory of Operations ===
	'''(c) Mark Spaeth 1999'''		'''(c) Mark Spaeth 1999'''

Line 19:		Line 19:
	VBLANK is generated by a flipflop at 5M. VBLANK is cleared when 16V goes high when 32V, 64V, and 128V, near the end of the count sequence. It is reset when 16H goes high when 32V, 64V, and 128V are all low near the beginning of the count sequence. The vertical blanking period lasts for 38 HSYNC cycles leaving 224 counts for data (thus the 224 line vertical resolution).		VBLANK is generated by a flipflop at 5M. VBLANK is cleared when 16V goes high when 32V, 64V, and 128V, near the end of the count sequence. It is reset when 16H goes high when 32V, 64V, and 128V are all low near the beginning of the count sequence. The vertical blanking period lasts for 38 HSYNC cycles leaving 224 counts for data (thus the 224 line vertical resolution).

	=== <p>~~'''~~Memory Map~~'''~~</p> ===		=== <p>Memory Map</p> ===

	Sure there's more to it, but this is all the video system cares about.		Sure there's more to it, but this is all the video system cares about.
Line 31:		Line 31:
	Byte 1: Color Code		Byte 1: Color Code

	=== <p>~~'''~~Sync Bus Controller~~'''~~</p> ===		=== <p>Sync Bus Controller</p> ===

	The sync bus controller interfaces the external devices to the processor. The address and data bus are connected to the roms directly, but for ram and IO port access the sync bus controller gets in the way. An important thing to note is that the 6M* input to the SBC trails the 6Mhz used to generate the timing clocks by 1/3 phase, so the edge occurs during each level of 1H. The /CS line is asserted during a /MREQ with A14 high, during a non-refresh cycle (/RFSH high).		The sync bus controller interfaces the external devices to the processor. The address and data bus are connected to the roms directly, but for ram and IO port access the sync bus controller gets in the way. An important thing to note is that the 6M* input to the SBC trails the 6Mhz used to generate the timing clocks by 1/3 phase, so the edge occurs during each level of 1H. The /CS line is asserted during a /MREQ with A14 high, during a non-refresh cycle (/RFSH high).
Line 37:		Line 37:
	To handle interrupts, Pacman uses the I interrupt regiester to store the high 8 bits of the interrupt vector address and writes the low 8 bits to 0x00, which stores it in the register at U7. During a mode 0 interrupt, /IORQ and /M1 are asserted, and the stored value is put back onto the data bus, and used as the low 8 bits of the of interrupt vector.		To handle interrupts, Pacman uses the I interrupt regiester to store the high 8 bits of the interrupt vector address and writes the low 8 bits to 0x00, which stores it in the register at U7. During a mode 0 interrupt, /IORQ and /M1 are asserted, and the stored value is put back onto the data bus, and used as the low 8 bits of the of interrupt vector.

	=== <p>~~'''~~VRAM Addresser~~'''~~</p> ===		=== <p>VRAM Addresser</p> ===

	The VRAM addresser determines the address to be accessed by the video output circuitry based on the values of the horizontal and vertical timing signals. The address is enabled by /2H. When 2H is low, the CPU controls the bus. When 2H is high, the video generator controls it.		The VRAM addresser determines the address to be accessed by the video output circuitry based on the values of the horizontal and vertical timing signals. The address is enabled by /2H. When 2H is low, the CPU controls the bus. When 2H is high, the video generator controls it.

Brad at 03:01, 14 August 2012

2012-08-14T03:01:42Z

← Older revision		Revision as of 11:01, 14 August 2012
Line 1:		Line 1:
	== Pacman Video Circuitry Theory of Operations ==		== Pacman Video Circuitry Theory of Operations ==
	(c) Mark Spaeth 1999		'''(c) Mark Spaeth 1999'''

	<p>After searching the net for info while fixing a stack of dead pacman boards, I couldn't find any documentation on the video circuitry. This document is an attempt to rectify the problem. Since pacman uses a rotated monitor, the term horizontal will refer to things that appear on the vertical axis and vice-versa, so that the description will match the labeling on the		<p>After searching the net for info while fixing a stack of dead pacman boards, I couldn't find any documentation on the video circuitry. This document is an attempt to rectify the problem. Since pacman uses a rotated monitor, the term horizontal will refer to things that appear on the vertical axis and vice-versa, so that the description will match the labeling on the

Brad at 03:01, 14 August 2012

2012-08-14T03:01:32Z

← Older revision		Revision as of 11:01, 14 August 2012
Line 1:		Line 1:
	~~<p>~~== Pacman Video Circuitry Theory of Operations ==~~</p>~~		== Pacman Video Circuitry Theory of Operations ==
	(c) Mark Spaeth 1999~~</p>~~		(c) Mark Spaeth 1999

	<p>After searching the net for info while fixing a stack of dead pacman boards, I couldn't find any documentation on the video circuitry. This document is an attempt to rectify the problem. Since pacman uses a rotated monitor, the term horizontal will refer to things that appear on the vertical axis and vice-versa, so that the description will match the labeling on the		<p>After searching the net for info while fixing a stack of dead pacman boards, I couldn't find any documentation on the video circuitry. This document is an attempt to rectify the problem. Since pacman uses a rotated monitor, the term horizontal will refer to things that appear on the vertical axis and vice-versa, so that the description will match the labeling on the

Brad at 03:01, 14 August 2012

2012-08-14T03:01:16Z

← Older revision		Revision as of 11:01, 14 August 2012
Line 1:		Line 1:
	<p>		<p>== Pacman Video Circuitry Theory of Operations ==</p>
	== Pacman Video Circuitry~~<br>~~

	Theory of Operations ==

	</p~~><br~~>
	(c) Mark Spaeth 1999</p>		(c) Mark Spaeth 1999</p>

	<p>After searching the net for info while fixing a stack of dead pacman boards, I couldn't find any documentation on the video circuitry. This document is an attempt to rectify the problem. Since pacman uses a rotated monitor, the term horizontal will refer to things that appear on the vertical axis and vice-versa, so that the description will match the labeling on the		<p>After searching the net for info while fixing a stack of dead pacman boards, I couldn't find any documentation on the video circuitry. This document is an attempt to rectify the problem. Since pacman uses a rotated monitor, the term horizontal will refer to things that appear on the vertical axis and vice-versa, so that the description will match the labeling on the
	schematics (not just to confuse you).</p>~~<br>~~		schematics (not just to confuse you).</p>


	=== Sync and Timing Signal Generation ===		=== Sync and Timing Signal Generation ===