Pacman Board Theory

Pacman Video Circuitry Theory of Operations

(c) Mark Spaeth 1999

After searching the net for info while fixing a stack of dead pacman boards, I couldn't find any documentation on the video circuitry. This document is an attempt to rectify the problem. Since pacman uses a rotated monitor, the term horizontal will refer to things that appear on the vertical axis and vice-versa, so that the description will match the labeling on the schematics (not just to confuse you).

Sync and Timing Signal Generation

The count sequences for the horizontal and vertical timing signals are listed at the end.

The horizontal timing and sync signals are generated from the 6Mhz clock using the chips at 2P, 3R, 3S, and 8C. The system-wide 6Mhz timing signal clocks the 7474 flipflop at 8C to generate the 3Mhz 1H signal, which controls the timing of each horizontal pixel. The 74161 counter at 3R is enabled by 1H and generates the 2H, 4H, 8H, and 16H signals each at half the frequency of the previous signal. The carryout of of 3R is asserted when all 4 counter bits are one, and enables the counter at 3S which generates 32H, 64H, 128H, and /256H. The NOR at 2P inverts the carrout of 3S which is used as the load signal for 3R and 3S that modifies the count sequence. Instead of rolling the counters (including /256H down to 1H) back to 000000000 after 111111111, the load sets the count to 010000001 after 111111110, yielding a 382-count period for the horizontal circuitry. Note that 3Mhz / 382 gives an approximate 16kHz period.

The horizontal blanking signals are generated in 2P, 3N, and 3P. The NOR at 2P inverts the /256H signal and uses it as the (active low) clear signal for the flipflop at 3N (ie. when /256H is one, the output of the flipflop is always zero). The flipflip is set to one when 16H goes high for the first time after the count rolls back to 010000001. It is cleared again on the rising edge of 16H when 32H and 64H are both high. This yields a 96-count blanking interval, and a 286-count data interval (so the actual resolution is 286 pixels, not 288 as most documentation says).

The /HSYNC signal is generated at 3N. HBLANK presets the second flipflip at 3N, forcing /HSYNC high outside of the blanking period. The output is cleared the first time 16H goes high after the start of the blanking period and is cleared on the rising edge of 16H when 64H is high, generating a 32-count sync period.

The vertical timing signals are generated from the HSYNC signal using the chips at 2P, 2R, 2S, and 5M. The 7474 at 5M is clocked by HSYNC to generated the 1V signal. 2V, 4V, 8V, and 16V are generated by the 74161 at 2R that is enabled by 1V. 32V, 64V, 128V, and ~VSYNC are generated by the 74161 at 2S that is enabled by the carryout of 2R. The carryout of 2S is inverted by the NOR at 2P, and is used as the load signal for 2R and 2S. This makes the count (including 1V) to roll from 111111110 to 011111001, yielding a 262-count period. The ~VSYNC signals is low for 7 counts at the beginning of the count sequence.

VBLANK is generated by a flipflop at 5M. VBLANK is cleared when 16V goes high when 32V, 64V, and 128V, near the end of the count sequence. It is reset when 16H goes high when 32V, 64V, and 128V are all low near the beginning of the count sequence. The vertical blanking period lasts for 38 HSYNC cycles leaving 224 counts for data (thus the 224 line vertical resolution).

Memory Map

Sure there's more to it, but this is all the video system cares about.

0000-3fff ROM 4000-43ff Video Ram (screen background character codes) 4400-47ff Color Ram (screen background color codes) 4c00-4cef Scratch Ram 4cf0-4cff Sprite Ram Byte 0: Sprite Code <7:2>, X Flip <1>, Y Flip <0> Byte 1: Color Code

Sync Bus Controller

The sync bus controller interfaces the external devices to the processor. The address and data bus are connected to the roms directly, but for ram and IO port access the sync bus controller gets in the way. An important thing to note is that the 6M* input to the SBC trails the 6Mhz used to generate the timing clocks by 1/3 phase, so the edge occurs during each level of 1H. The /CS line is asserted during a /MREQ with A14 high, during a non-refresh cycle (/RFSH high).

To handle interrupts, Pacman uses the I interrupt regiester to store the high 8 bits of the interrupt vector address and writes the low 8 bits to 0x00, which stores it in the register at U7. During a mode 0 interrupt, /IORQ and /M1 are asserted, and the stored value is put back onto the data bus, and used as the low 8 bits of the of interrupt vector.

VRAM Addresser

The VRAM addresser determines the address to be accessed by the video output circuitry based on the values of the horizontal and vertical timing signals. The address is enabled by /2H. When 2H is low, the CPU controls the bus. When 2H is high, the video generator controls it.

When /256H is high, normal screen data is being output. The low 10 bits of the VRAM address are determined by [128V, 64V, 32V, 16V, 8V, 128H, 64H, 32H, 16H, 8H]. The high bit is always 0, and the 11th bit is 4H, so that background sprite numbers are read on one cycle (4N), and the color is read the next (4P). 4V, 2V, 1V, 4H, 2H, and 1H are not used in the address directly, since they are not needed, since the sprites are 8x8 pixels. The data addressed here is

When /256H is low, the outputs are determined by whether 16H==32H==64H. If all three are euap, the address is [0, 4H, 64H, 64H, 64H, 64H, 8H, 128V, 64V, 32V, 16V, 8V]. This occurs when drawing either the score area or level area. The address is scrambled to use the screen ram area that is not used by the screen itself.

During VBLANK, the VRA addresses 4FF2-4FFD, where the motion object sprite numbers and color codes are stored. Note that due to the addressing, only 6 of the 8 sprite positions can be used.

4004-403B : Score area 4040-43BF : Screen area 43C4-43FB : Level area

Horizontal Timing Signals

~ (382 lines, 96 blanked, 286 data)
21 ~~
52631 HHH
684268421 BBS

010000001 011
010000010 011
010000011 011
010000100 011
010000101 011
010000110 011
010000111 011
010001--- 011
010010--- 101
010011--- 101
010100--- 101
010101--- 101
010110--- 100
010111--- 100
011000--- 100
011001--- 100
011010--- 101
011011--- 101
011100--- 101
011101--- 101
011110--- 011
011111--- 011
100000--- 011
100001--- 011
100010--- 011
100011--- 011
100100--- 011
100101--- 011
100110--- 011
100111--- 011
101000--- 011
101001--- 011
101010--- 011
101011--- 011
101100--- 011
101101--- 011
101110--- 011
101111--- 011
100000--- 011
100001--- 011
100010--- 011
100011--- 011
100100--- 011
100101--- 011
100110--- 011
101111--- 011
111000--- 011
111001--- 011
111010--- 011
111011--- 011
111100--- 011
111101--- 011
111110--- 011
111111000 011
111111001 011
111111010 011
111111011 011
111111100 011
111111101 011
111111110 011

Vertical Timing Signals

~1 ~ (262 rows, 38 blanked, 224 normal)
V2631 V
S84268421 B

011111001 0
011111010 0
011111011 0
011111100 0
011111101 0
011111110 0
011111111 0
100000--- 0
100001--- 0
100010--- 1 0000 0100 00000
100011--- 1
100100--- 1
100101--- 1
100110--- 1
100111--- 1
101000--- 1
101001--- 1
101010--- 1
101011--- 1
101100--- 1
101101--- 1
101110--- 1
101111--- 1
110000--- 1
110001--- 1
110010--- 1
110011--- 1
110100--- 1
110101--- 1
110110--- 1
110111--- 1
111000--- 1
111001--- 1
111010--- 1
111011--- 1
111100--- 1
111101--- 1 0011 1011 1111
111110--- 0
111111000 0
111111001 0
111111010 0
111111011 0
111111100 0
111111101 0
111111110 0

Sprites:

4ff0-4fff 8 pairs of two bytes:

 Byte 1: sprite image number (bits 2-7), Y flip (bit 0), X flip (bit 1);

 Byte 2: the color #

0100 1111 1111 x x x x

              ^   ^   ^   ^

              H64 H32 H16 H4 (?)

Addressed from VRA during:

~256H = 0 (74257 select input)
16H != 32H or 32H != 64H (74157 select input)