Difference between revisions of "PCB Repair Logs Pacman 2 1"
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<p>'''Before we start'''</p> | <p>'''Before we start'''</p> | ||
<p>'''SBC'''=Sync Bus Controller<br> | <p>'''SBC'''=Sync Bus Controller<br> | ||
'''VRA'''=VRAM Addresser</p | '''VRA'''=VRAM Addresser</p> | ||
<p>The sync bus controller interfaces the external devices to the processor. The address and data bus are connected to the roms directly, but for ram and IO port access the sync bus controller gets in the way. An important thing to note is that the 6M* input to the SBC trails the 6Mhz used to generate the timing clocks by 1/3 phase, so the edge occurs during each level of 1H. The /CS line is asserted during a /MREQ with A14 high, during a non-refresh cycle (/RFSH high).</p> | <p>The sync bus controller interfaces the external devices to the processor. The address and data bus are connected to the roms directly, but for ram and IO port access the sync bus controller gets in the way. An important thing to note is that the 6M* input to the SBC trails the 6Mhz used to generate the timing clocks by 1/3 phase, so the edge occurs during each level of 1H. The /CS line is asserted during a /MREQ with A14 high, during a non-refresh cycle (/RFSH high).</p> | ||
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<p>During a mode 0 interrupt, /IORQ and /M1 are asserted, and the stored value is put back onto the data bus, and used as the low 8 bits of the of interrupt vector.</p> | <p>During a mode 0 interrupt, /IORQ and /M1 are asserted, and the stored value is put back onto the data bus, and used as the low 8 bits of the of interrupt vector.</p> | ||
The VRAM addresser determines the address to be accessed by the video output circuitry based on the values of the horizontal and vertical timing signals. The address is enabled by /2H. When 2H is low, the CPU controls the bus. When 2H is high, the video generator controls it. | |||
When /256H is high, normal screen data is being output. The low 10 bits of the VRAM address are determined by [128V, 64V, 32V, 16V, 8V, 128H, 64H, 32H, 16H, 8H]. The high bit is always 0, and the 11th bit is 4H, so that background sprite numbers are read on one cycle (4N), and the color is read the next (4P). 4V, 2V, 1V, 4H, 2H, and 1H are not used in the address directly, since they are not needed, since the sprites are 8x8 pixels. | |||
The data addressed here is When /256H is low, the outputs are determined by whether 16H==32H==64H. If all three are euap, the address is [0, 4H, 64H, 64H, 64H, 64H, 8H, 128V, 64V, 32V, 16V, 8V]. This occurs when drawing either the score area or level area. The address is scrambled to use the screen ram area that is not used by the screen itself. | |||
During VBLANK, the VRA addresses 4FF2-4FFD, where the motion object sprite numbers and color codes are stored. Note that due to the addressing, only 6 of the 8 sprite positions can be used. | |||
Information was taken from Pac theory document attached. | |||
Its interesting to note that all 3 pac boards that I have had have all had the "PacGal" hack done. PacGal being the bootleg version of Ms Pacman. The hack consists of 5 2532's with a 2716 on the top board and 4 2716's on the bottom board. This is one of my favorite boards, the SBC and VBA are intergrated into the board itself so no rider boards,. There are 2 edge connectors, a 18 pin same pinout as the Pac 3 and a 24 pin connection. | |||
When I made my harness I fired her up and was greeted with a blue screen. If you look closely you can see horizontal moving rectangles which are infact the characters. | |||
[[File:Pac2-1-screen.jpg]] | |||
Revision as of 09:12, 14 August 2012
Pacman 2 in 1 (Bootleg)
Repairer: Arcade King
Forum Thread: Pacman 2 in 1 PCB Repair
This was the pic of the board on the E-bay, Chris the guy who won it paid I think like 95 pounds for it or something.
Notice the Jamma adapter, it magically went missing when I picked up the board off JP.
Before we start
SBC=Sync Bus Controller
VRA=VRAM Addresser
The sync bus controller interfaces the external devices to the processor. The address and data bus are connected to the roms directly, but for ram and IO port access the sync bus controller gets in the way. An important thing to note is that the 6M* input to the SBC trails the 6Mhz used to generate the timing clocks by 1/3 phase, so the edge occurs during each level of 1H. The /CS line is asserted during a /MREQ with A14 high, during a non-refresh cycle (/RFSH high).
To handle interrupts, Pacman uses the I interrupt regiester to store the high 8 bits of the interrupt vector address and writes the low 8 bits to 0x00, which stores it in the register at U7.
During a mode 0 interrupt, /IORQ and /M1 are asserted, and the stored value is put back onto the data bus, and used as the low 8 bits of the of interrupt vector.
The VRAM addresser determines the address to be accessed by the video output circuitry based on the values of the horizontal and vertical timing signals. The address is enabled by /2H. When 2H is low, the CPU controls the bus. When 2H is high, the video generator controls it.
When /256H is high, normal screen data is being output. The low 10 bits of the VRAM address are determined by [128V, 64V, 32V, 16V, 8V, 128H, 64H, 32H, 16H, 8H]. The high bit is always 0, and the 11th bit is 4H, so that background sprite numbers are read on one cycle (4N), and the color is read the next (4P). 4V, 2V, 1V, 4H, 2H, and 1H are not used in the address directly, since they are not needed, since the sprites are 8x8 pixels.
The data addressed here is When /256H is low, the outputs are determined by whether 16H==32H==64H. If all three are euap, the address is [0, 4H, 64H, 64H, 64H, 64H, 8H, 128V, 64V, 32V, 16V, 8V]. This occurs when drawing either the score area or level area. The address is scrambled to use the screen ram area that is not used by the screen itself.
During VBLANK, the VRA addresses 4FF2-4FFD, where the motion object sprite numbers and color codes are stored. Note that due to the addressing, only 6 of the 8 sprite positions can be used.
Information was taken from Pac theory document attached.
Its interesting to note that all 3 pac boards that I have had have all had the "PacGal" hack done. PacGal being the bootleg version of Ms Pacman. The hack consists of 5 2532's with a 2716 on the top board and 4 2716's on the bottom board. This is one of my favorite boards, the SBC and VBA are intergrated into the board itself so no rider boards,. There are 2 edge connectors, a 18 pin same pinout as the Pac 3 and a 24 pin connection.
When I made my harness I fired her up and was greeted with a blue screen. If you look closely you can see horizontal moving rectangles which are infact the characters.
