Pacman Board Theory

Pacman Video Circuitry
Theory of Operations

(c) Mark Spaeth 1999

After searching the net for info while fixing a stack of dead pacman boards, I couldn't find any documentation on the video circuitry. This document is an attempt to rectify the problem. Since pacman uses a rotated monitor, the term horizontal will refer to things that appear on the vertical axis and vice-versa, so that the description will match the labeling on the schematics (not just to confuse you).

Sync and Timing Signal Generation

The count sequences for the horizontal and vertical timing signals are listed at the end.

The horizontal timing and sync signals are generated from the 6Mhz clock using the chips at 2P, 3R, 3S, and 8C. The system-wide 6Mhz timing signal clocks the 7474 flipflop at 8C to generate the 3Mhz 1H signal, which controls the timing of each horizontal pixel. The 74161 counter at 3R is enabled by 1H and generates the 2H, 4H, 8H, and 16H signals each at half the frequency of the previous signal. The carryout of of 3R is asserted when all 4 counter bits are one, and enables the counter at 3S which generates 32H, 64H, 128H, and /256H. The NOR at 2P inverts the carrout of 3S which is used as the load signal for 3R and 3S that modifies the count sequence. Instead of rolling the counters (including /256H down to 1H) back to 000000000 after 111111111, the load sets the count to 010000001 after 111111110, yielding a 382-count period for the horizontal circuitry. Note that 3Mhz / 382 gives an approximate 16kHz period.

The horizontal blanking signals are generated in 2P, 3N, and 3P. The NOR at 2P inverts the /256H signal and uses it as the (active low) clear signal for the flipflop at 3N (ie. when /256H is one, the output of the flipflop is always zero). The flipflip is set to one when 16H goes high for the first time after the count rolls back to 010000001. It is cleared again on the rising edge of 16H when 32H and 64H are both high. This yields a 96-count blanking interval, and a 286-count data interval (so the actual resolution is 286 pixels, not 288 as most documentation says).

The /HSYNC signal is generated at 3N. HBLANK presets the second flipflip at 3N, forcing /HSYNC high outside of the blanking period. The output is cleared the first time 16H goes high after the start of the blanking period and is cleared on the rising edge of 16H when 64H is high, generating a 32-count sync period.

The vertical timing signals are generated from the HSYNC signal using the chips at 2P, 2R, 2S, and 5M. The 7474 at 5M is clocked by HSYNC to generated the 1V signal. 2V, 4V, 8V, and 16V are generated by the 74161 at 2R that is enabled by 1V. 32V, 64V, 128V, and ~VSYNC are generated by the 74161 at 2S that is enabled by the carryout of 2R. The carryout of 2S is inverted by the NOR at 2P, and is used as the load signal for 2R and 2S. This makes the count (including 1V) to roll from 111111110 to 011111001, yielding a 262-count period. The ~VSYNC signals is low for 7 counts at the beginning of the count sequence.

VBLANK is generated by a flipflop at 5M. VBLANK is cleared when 16V goes high when 32V, 64V, and 128V, near the end of the count sequence. It is reset when 16H goes high when 32V, 64V, and 128V are all low near the beginning of the count sequence. The vertical blanking period lasts for 38 HSYNC cycles leaving 224 counts for data (thus the 224 line vertical resolution).